Udemy - Digital Timing Basics For Vlsi Interview and Soc Design torrent

Digital Timing Basics For Vlsi Interview & Soc Design
https://DevCourseWeb.com

MP4 | Video: h264, 1280x720 | Audio: AAC, 44.1 KHz
Language: English (US) | Size: 826.03 MB | Duration: 4h 1m

A VLSI Course on Timing Concepts frequently used in Physical Design (Static Timing Analysis - STA), RTL & Circuit Design

What you'll learn
Basics of Flop & Latch Timings
Set-up, Hold, Clock to Q, Clock Skew
Set-up & Hold violation checks
Set-up & Hold violation fixes
Latency Minimization
Set-up & Hold Margin in Digital Ckts
Min & Max Path Analysis
Clock Gating
F-V Curve in SoC

Requirements
Knowledge of Flop functionality will suffice