Hyde J SuperSpeed Device Design By Example 2014 torrent

Textbook in PDF format

SuperSpeed USB is More Than Just Higher Speed
Dual bus architecture.
Review of USB 2.0 operation
USB 3.0 enhancements
USB 3.0 power management
A SuperSpeed Device Hardware Platform
SuperSpeed Explorer Board
A Robust Software Base
Multi-threading RTOS 101
Operation from RESET
API Overview
Key ThreadX features
Thread communication
Thread communications using a queue
DMA Programming Model
Power Aware Programming
FX3 Power Mode Handling
FX3 Firmware Development
Project Template
Adding Console_In
Adding Paramter Input
Display Program Threads
Display Stack Usage
Adding an Error Indicator
Adding RTOS Visibility
Exploring the FX3 Low Speed Peripherals
Connecting the CPLD board
Dual Console Project
SPI Example
SuperSpeed USB communications
Keyboard Example
CDC Example
Debug Console Over USB
Cypress USB examples
BulkLoop Firmware
Streamer firmware
Low speed IO examples
Other examples
PC Host Software Development
CollectData
Cypress PC Utilities
BulkLoop Utility
Streamer utility
USB Control Center
Commercial USB Port Tester
FX3 Throughput Benchmark
How Benchmark works
The Producer/Consumer model
The Low Level unmanaged C++ level
Producers
Consumers
OverlappedIO
Mid-level Managed C++ layer
USB Engine
Getting Started With High-Speed IO.
First GPIF Project
Setting up GPIF II
Setting up a DMA Channel
Design Stage 1
Design stage 2
Design stage 3
Completed Design – a Logic Analyzer
Moving Real Data, Part 1.
Chapter 11: Moving Real Data, Part 2.
Slave FIFO Design
Third Party Products
FIFO Master Design.
Combined master read and write
Master FX3 FIFO connected to a Slave FX3 FIFO
Load and Run
Programming the CPLD
How the CPLD Programmer Works
Developing your own CPLD Code
Introduction To Verilog
FX3 Lite (Boot) Firmware Library
Building an I2C Debug Console
FX3 Family Members
FX3S designed for storage application
CX3 designed for video capture applications